The present invention relates, in general, to electronics and, more particularly, to methods of forming semiconductor devices and structure.
Circuit elements such as capacitors, resistors, and inductors are used in a variety of applications including telecommunications, automotive, computational, portable applications, power distribution systems, etc. Many of these types of systems include power converters that have a high voltage portion and a lower voltage portion and convert voltages from a high voltage level to a lower voltage level. In these types of applications, it may be desirable to monitor electrical parameters on the high voltage portion of the converter. High voltage capacitors or a network of capacitors have been used as dynamic sensing elements to monitor electrical signals on the high voltage portion of the converter. Capacitors may be configured to block direct current (DC) current voltage level while sensing dynamic voltage changes. In the past, these types of capacitor configurations have been expensive to implement and have been external to monolithically manufactured controller circuitry.
Accordingly, there is a need for a method and structure that permits monitoring of high power signals. It is desirable for the method and structure to be cost and time efficient to implement.
FIG. 1 is an isometric view of a circuit element in accordance with an embodiment of the present invention;
FIG. 2 is a cross-sectional view of the circuit element shown FIG. 1;
FIG. 3 is a circuit schematic of the circuit element shown in FIG. 1;
FIG. 4 is an isometric view of a circuit element in accordance with another embodiment of the present invention;
FIG. 5 is a cross-sectional view taken along section line 5-5 of the circuit element shown FIG. 4;
FIG. 6 is a cross-sectional view taken along section line 6-6 of the circuit element shown FIG. 4;
FIG. 7 is a circuit schematic of the circuit element shown in FIG. 4;
FIG. 8 is a cross-sectional view of a circuit element at an early stage of manufacture in accordance with another embodiment of the present invention;
FIG. 9 is a cross-sectional view of the circuit element of FIG. 8 at a later stage of manufacture;
FIG. 10 is a cross-sectional view of the circuit element of FIG. 9 at a later stage of manufacture;
FIG. 11 is a cross-sectional view of the circuit element of FIG. 10 at a later stage of manufacture;
FIG. 12 is a cross-sectional view of the circuit element of FIG. 11 at a later stage of manufacture;
FIG. 13 is a cross-sectional view of the circuit element of FIG. 12 at a later stage of manufacture;
FIG. 14 is a cross-sectional view of the circuit element of FIG. 13 at a later stage of manufacture;
FIG. 15 is a cross-sectional view of the circuit element of FIG. 14 at a later stage of manufacture;
FIG. 16 is a cross-sectional view of the circuit element of FIG. 15 at a later stage of manufacture;
FIG. 17 is a cross-sectional view of the circuit element of FIG. 16 at a later stage of manufacture;
FIG. 18 is a cross-sectional view of the circuit element of FIG. 17 at a later stage of manufacture;
FIG. 19 is a cross-sectional view of the circuit element of FIG. 18 at a later stage of manufacture;
FIG. 20 is a cross-sectional view of the circuit element of FIG. 19 at a later stage of manufacture;
FIG. 21 is a cross-sectional view of the circuit element of FIG. 20 at a later stage of manufacture;
FIG. 22 is a cross-sectional view of a circuit element at an early stage of manufacture in accordance with another embodiment of the present invention;
FIG. 23 is a top view of the circuit element of FIG. 22;
FIG. 24 is a cross-sectional view of the circuit element of FIGS. 22 and 23 at a later stage of manufacture in accordance with another embodiment of the present invention;
FIG. 25 is a top view of the circuit element of FIG. 24;
FIG. 26 is a cross-sectional view of the circuit element of FIGS. 24 and 25 at a later stage of manufacture in accordance with another embodiment of the present invention;
FIG. 27 is a top view of the circuit element of FIG. 26;
FIG. 28 is a cross-sectional view of the circuit element of FIGS. 26 and 27 at a later stage of manufacture in accordance with another embodiment of the present invention;
FIG. 29 is a top view of the circuit element of FIG. 28;
FIG. 30 is a cross-sectional view of the circuit element of FIGS. 28 and 29 at a later stage of manufacture in accordance with another embodiment of the present invention; and
FIG. 31 is a circuit schematic of the circuit element shown in FIG. 30.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference characters in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or an anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain n-channel or p-channel devices, or certain n-type or p-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention. It should be noted that a doped region may be referred to as a dopant region. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action and the initial action. The use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position. However, as is well known in the art there are always minor variances that prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to about ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are regarded as reasonable variances from the ideal goal of being exactly as described.